1. Field of the Invention
The present invention relates generally to electronic oscillators and more particularly to signal-controlled ring oscillators.
2. Description of the Related Art
Stable signal-controlled oscillators find use in a variety of integrated circuit systems, e.g., phase locked loops, counters, frequency dividers and frequency multipliers. A popular integrated-circuit oscillator structure is a ring oscillator which couples a plurality of time-delay stages in a closed feedback ring. Because this configuration is simple, does not require large frequency-determining elements (e.g., inductors and capacitors) and is easily realized in a differential configuration, it is particularly suited for integrated circuit fabrication processes and systems.
FIG. 1 illustrates a conventional ring oscillator 20 (e.g., see FIG. 7 of Reynolds, David, "A 320 MHz CMOS Triple 8 bit DAC with On-Chip PLL and Hardware Cursor", IEEE Journal of Solid-State Circuits, Vol. 29, No. 12, pp. 1545-1551) which includes n differential time-delay stages 22 that are serially connected to form a closed feedback ring 23. In this configuration, n-1 stages are coupled to have input and output signals of the same polarity and one stage is coupled to have input and output signals of different polarities (i.e., this latter stage is coupled to provide signal inversion).
If the output signal of each stage 22 is delayed from its input signal by a time delay .tau..sub.D, then the oscillator's signal at an output port 24 will have a frequency f given by ##EQU1## The time delay .tau..sub.D is typically a function of a control voltage V.sub.C which is carried through a control path 26 to each stage 22 as shown in FIG. 1. In addition, a bias circuit 27 provides a current bias voltage V.sub.IB which is carried through a bias path 28 to each stage.
Particular use of the control voltage V.sub.C and current bias voltage V.sub.IB is shown in the schematic diagram of FIG. 2 which details an exemplary time-delay stage 22. The stage has a differential amplifier in the form of a differential pair 30 of transistors 32 that are coupled between a differential input 34 and a differential output 36. The differential pair 30 joins a pair 40 of load transistors 42 and a current source in the form of a current-supply transistor 38. The load transistors are connected to ground and transistor 38 is connected to a power supply voltage V.sub.DD.
In an exemplary realization, the time-delay stage is realized in a complementary metal-oxide semiconductor (CMOS) structure so that the transistors are metal-oxide field-effect transistors (MOSFETs). Transistors 32 and 38 are p-channel (PMOSFETs) and the load transistors 42 are n-channel (NMOSFETs). The gate of the current-supply transistor 38 is arranged to receive the current bias voltage V.sub.IB at a bias port 44 (this port is connected to the bias path 28 of FIG. 1). The gates of the differential pair 30 are coupled to the differential input 34 and their drains are coupled to the output 36. The gates of the load transistors 42 are connected to receive a control voltage V.sub.C at a control port 46 (that is connected to the control path 26 of FIG. 1) and these transistors are drain-coupled with the differential pair 30.
An output signal amplitude at the output port 36 is determined by the amount of current that is switched across the load transistors 42. Because this current is a function of the current bias voltage V.sub.IB, adjustment of this voltage can realize a selected signal amplitude at the differential output 36. This signal amplitude is also the drain-to-source voltage V.sub.DS of the load transistors 42 which must be less than V.sub.GS -V.sub.t in order to operate the load transistors in their triode region (V.sub.t being the MOSFET threshold voltage). Because V.sub.GS of the load transistors is the control voltage V.sub.C, the current bias voltage V.sub.IB is set in the bais circuit 27 to insure that V.sub.DS .ltoreq.V.sub.C -V.sub.t.
An understanding of the operation of the time-delay stage 22 is enhanced by consideration of the equivalent circuit 50 of FIG. 3 that models the stage. This equivalent circuit has a current source 52 in series with a parallel combination of a variable resistor 54V and a capacitor 56. The current source 52 represents the current I.sub.DS.sbsb.38 supplied by the current-supply transistor (38 in FIG. 2), the variable resistor 54V represents the variable resistance R.sub.V of either of the triode-biased load transistors (42 in FIG. 2) and the capacitor 56 represents the input capacitance C.sub.input of the following time-delay stage (in the ring arrangement of FIG. 1) plus any stray parasitic capacitance. This capacitance is the sum of the input capacitances (e.g., gate capacitance and drain junction capacitance) of the differential pair (30 in FIG. 2).
The equivalent circuit 50 shows that signals at the output port 36 of FIG. 2 change with a time constant RC so that the output voltage V.sub.o is given by ##EQU2##
The output polarity of the time-delay stage 22 will change when the voltage of equation (2) reaches 50% of its final voltage of I.sub.DS.sbsb.38 R.sub.V so that the time delay .tau..sub.D is approximately 0.693R.sub.V C.sub.input. Because the load transistors 42 are in their triode region, varying the control voltage V.sub.C changes the value of R.sub.V and, hence, the value of the time delay .tau..sub.D. In accordance with equation (1), the frequency of the ring oscillator 20 of FIG. 1 is thus a function of the control voltage V.sub.C at the control port (46 in FIG. 2) of each time-delay stage.
Unfortunately, the resistance of MOSFETs in their triode region is temperature sensitive as shown by the relationship of ##EQU3## in which .mu. is the channel carrier mobility, C.sub.ox is gate oxide capacitance per unit area, W/L is the channel width-to-length ratio, and V.sub.GS is gate-to-source voltage. Because mobility and threshold voltage are significantly affected by temperature, equation (3) indicates that the resistance R.sub.V is temperature sensitive and, accordingly, the time delay .tau..sub.D and the frequency f of the ring oscillator 20 of FIG. 1 are also temperature sensitive.
In addition to its temperature sensitivity, the ring oscillator 20 of FIG. 1 will also be sensitive to its supply voltage V.sub.DD and to variations in fabrication processes unless care is taken to decrease these sensitivities.